1. Field of the Invention
The present invention relates to a multiprocessor system architecture and more particularly to method and apparatus by which the processors communicate with one another.
2. Description of the Prior Art
Several types of multiprocessor system architectures have been suggested. Bus communication architectures are among those more commonly used because of the good performances they offer at relatively low cost and without undue complexity. In such architectures, the several processors are connected to one another and to one or more memories through a communication bus accessible in a time sharing manner. An example of such a bus system architecture is disclosed by U.S. Pat. No. 4,404,628.
The communication bus of such architectures constitutes a set of leads enabling each of the processors to communicate with one or more common or "shared" memories and with one or more common peripherals.
The communication mechanism, or method, of communication between processors and peripherals is generally direct, that is, the processor selects, by suitable commands, a peripheral unit and if that unit is free, or available, the processor sends suitable commands to it. The processor, therefore, operates as the "master" with respect to peripheral units which operate as "slaves".
Peripheral units may initiate communications with the master processor by interrupt mechanisms, that is, the peripheral unit, which has a need to communicate information to a processor, generates an interrupt signal on an interrupt lead which is not part of the system bus. In due time, the processor which receives the interrupt signal, once the execution of current operations has been completed, or suspended, responds to the interrupt by "testing" with suitable commands the interrupting unit to identify the nature and the reasons for such interruption. This type of communication mechanism, both method and apparatus, between processors and peripherals units is effective but requires the assignment of the different roles of master and slave to a processor and the peripheral units respectively.
In the case of communication between processors, which can be a central unit, or CPU, or a peripheral unit control processor or "I/O processor", but which are however intended to operate in an autonomous manner and with equal rights to that of a CPU, or as masters, a different communication mechanism which does not require changes in the roles of the processors involved in the communication process is preferred. A mechanism, or method for accomplishing this is to provide communications through mailboxes in a shared memory which can be accessed by several processors. Memory areas, or mailboxes, are defined, with each mail box being dedicated to or connected with a given processor but accessible by all processors of the system.
Thus, a processor A, if it wants to communicate with a processor B, simply writes a message into the mailbox for processor B. How does processor B know that a message is present for it in its' mailbox, and how does processor A know that its message has been received by processor B? A solution taught by the prior art is polling, a procedure by which each processor periodically verifies the content of the mailbox. In other words, processor B periodically reads information stored in its mailbox to verify the presence of messages addressed to processor B. Likewise processor A may read the contents of processor B's mailbox to determine if processor B has received a message sent by A, as well as to periodically check its own mailbox to verify the presence of an answer message from B written into A's own mailbox. This process requires a considerable amount of time which degrades system performance essentially for two reasons: the first reason being that each processor has to spend time conducting polling operations, and the second reason being that, the polling operation requires a read memory operation and the use of the common bus to which the memory is connected. Thus, two fundamental common resources are used (memory and bus) which prevent their being used by the other processors, for example.
A process for signaling the presence of a message, very similar to the interrupt process, has therefore been associated with the use of mailboxes to provide communications between processors. Such a process is defined as a notify process. The already mentioned U.S. patent discloses an embodiment of such a process.
In the notify process, processor A, after writing a message into processor B's mailbox, generates a notify signal which is received and stored by processor B (for instance in a flip-flop). Thus, processor B does not have to conduct a memory polling operation to verify the presence of messages addressed to it, but only has to periodically verify the status of its notify flip-flop which does no require using system common resources. However, with this process, the problem of most effectively using the common resources of a system is only partially solved. The reason being that if processor A wants to determine if a message it sent to processor B has been received, processor A may go to the common memory to verify if its message has been read out of B's mailbox, or it can wait for an answer message from processor B, using the method of mailbox writing and notification similar to that already described. In both cases, it is evident that the use of common resources and the operation of one or both processors is required. An aspect that has to be considered is the handling, at program level, of notify signals, and the problem of eliminating interference in accessing shared resources such as mailboxes.
In the handling of programs in execution in multiprocessor systems, preemption operations are often used. With reference to the notify process, the preemption concept means that a message written into processor A's mailbox by processor B can be canceled if the receiving processor, processor A, has not yet taken any action with respect to the message in its mailbox. Processor B does this by sending a new message to be substituted for the message previously stored by it in A's mailbox. This may be required if during the execution of programs, the execution of an operation which was previously transmitted to processor A's mailbox and which was the subject of a notify signal, is no longer necessary or desirable. Preemption operations have been implemented in the art by having the sending processor read out the message previously written into the mailbox by it to verify that the message has not been considered by the receiving processor and thereafter the sending processor writes another message into the receiving processor's mailbox, and sends another notify signal.
It is clear that to carry out such verification operations, an access to memory is required which prevents other units from concurrently using the shared resources (bus and memory). To prevent interference in the access to common resources, the commonly adopted solution involves the use of a "Test and Set" instruction. A memory location, a mailbox, is coupled to, or associated, with each common resource. In such a location binary information is written to indicate if that resource is available, or is locked, or not available for use. A processor which wants to access a resource (mailbox) to write a message, must, first of all, verify that no processor is using that resource at the same instant. Therefore, before accessing the resource, a processor executes an indivisible read and write operation, Test & Set, of the memory location coupled, or associated with that resource.
Through such an operation, the processor reads out the preexisting contents of the location and immediately thereafter writes or rewrites information into that location and thus locks that resource. This operation is possible only in systems where the instruction Test & Set is one that can be executed, and, again, it requires the use of common resources (memory and bus) to prevent concurrent use by other units.